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document number: 67952 www.vishay.com s11-1003-rev. a, 23-may-11 1 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 8-ch/dual 4-ch high-performance cmos analog multiplexers dg408mil, dg409mil vishay siliconix description the dg408 is an 8 channel single-ended analog multiplexer designed to connect one of eight inputs to a common output as determined by a 3-bit binary address (a 0 , a 1 , a 2 ). the dg409 is a dual 4 channel differential analog multiplexer designed to connect one of four differential inputs to a common dual output as determined by its 2-bit binary address (a 0 , a 1 ). break-before-make switching action protects against momentary crosstalk between adjacent channels. an on channel conducts current equally well in both directions. in the off state each channel blocks voltages up to the power supply rails. an en able (en) function allows the user to reset the multiplexer/demu ltiplexer to all switches off for stacking several devices. all control inputs, address (a x ) and enable (en) are ttl compatible over the full specified operating temperature range. applications for the dg408, dg409 include high speed data acquisition, audio signal switching and routing, ate systems, and avionics. high performance and low power dissipation make them ideal for battery operated and remote instrumentation applications. designed in the 44 v silic on-gate cmos process, the absolute maximum voltage rati ng is extended to 44 v. additionally, single supply op eration is also allowed. an epitaxial layer prevents latchup. for additional information please see technical article ta201. features ? low on-resistance - r ds(on) : 100 ? ? low charge injection - q: 20 pc ? fast transition time - t trans : 160 ns ? low power - i supply : 10 a ? single supply capability ? 44 v supply max. rating ? ttl compatible logic benefits ? reduced switching errors ? reduced glitching ? improved data throughput ? reduced power consumption ? increased ruggedness ? wide supply ranges ( 5 v to 20 v) applications ? data acquisition systems ? audio signal routing ? ate systems ? battery powered systems ? high rel systems ? single supply systems ? medical instrumentation functional block diagram and pin configuration s 3 a 0 s 6 d s 4 a 1 s 8 s 7 en cerdip a 2 v- gnd s 1 v+ s 2 s 5 decoders/drivers 1 2 3 4 5 6 7 16 15 14 13 12 11 10 top view 89 dg408 cerdip 9 a 0 d a a 1 d b en gnd v- v+ s 1a s 1b s 2a s 2b s 3a s 3b s 4a s 4b decoders/drivers 1 2 3 4 5 6 7 16 15 14 13 12 11 10 top view 8 dg409
www.vishay.com document number: 67952 2 s11-1003-rev. a, 23-may-11 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 dg408mil, dg409mil vishay siliconix notes ?logic 0 = v al ? 0.8 v ?logic 1 = v ah ? 2.4 v ?x = do not care key en a 1 nc a 0 a 2 s 4 s 8 nc d s 7 320 1 2 19 912 11 10 13 4 g nd s 6 v+ nc s 5 v- s 3 s 1 nc s 2 5 8 6 7 18 17 14 16 15 lcc-20 d g 408 top view key en a 1 nc a 0 g nd s 4a d b nc d a s 4b 320 1 2 19 912 11 10 13 4 v+ s 3b s 1b nc s 2b v- s 3a s 1a nc s 2a 5 8 6 7 18 17 14 16 15 d g 409 lcc-20 top view flatpack top view 9 16 15 14 13 12 11 10 s 8 a 1 a 2 g nd v+ s 5 s 6 s 7 8 1 2 3 4 5 6 7 d a 0 en v- s 1 s 2 s 3 s 4 d g 408 flatpack top view 9 16 15 14 13 12 11 10 d b a 1 g nd v+ s 1b s 2b s 3b s 4b 8 1 2 3 4 5 6 7 d a a 0 en v- s 1a s 2a s 3a s 4a d g 409 truth table (dg408) a 2 a 1 a 0 en on switch xxx0none 0001 1 0011 2 0101 3 0111 4 1001 5 1011 6 1101 7 1111 8 truth table (dg409) a 1 a 0 en on switch xx0none 0011 0112 1013 1114
document number: 67952 www.vishay.com s11-1003-rev. a, 23-may-11 3 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 dg408mil, dg409mil vishay siliconix note ? block diagram and pi n configuration for fl at-pack 16 not shown. notes a. signals on s x , d x or in x exceeding v+ or v- will be clampe d by internal diodes. limit forward diode current to maximum current ratings. b. all leads soldered or welded to pc board. c. derate 12 mw/c above 75 c. d. derate 10 mw/c above 75 c. ordering information (hi-rel) part configuration temp. range package ordering part generic dscc number dg408 8:1 x 1 - 55 c to 125 c 16-pin cerdip dg408ak dg408ak - dg408ak-e3 dg408ak-e3 - 9204201ea dg408ak/883 5962-9204201mea lcc-20 92042012a dg408az/883 5962-9204201m2a 92042012c 5962-9204201m2c flat-pack 16 9204201xa dg408al/883 5962-9204201mxa 9204201xc 5962-9204201mxc dg409 4:1 x 2 - 55 c to 125 c 16-pin cerdip DG409AK DG409AK - DG409AK-e3 DG409AK-e3 - 9204202ea DG409AK/883 5962-9204202mea lcc-20 92042022a dg409az/883 5962-9204202m2a 92042022c 5962-9204202m2c flat-pack 16 9204202xa dg409al/883 5962-9204202mxa 9204202xc 5962-9204202mxc absolute maximum ratings parameter limit unit voltages referenced to v- v+ 44 v gnd 25 digital inputs a , v s , v d (v-) - 2 to (v+) + 2 or 20 ma, whichever occurs first current (any terminal) 30 ma peak current, s or d (pulsed at 1 ms, 10 % duty cycle max.) 100 storage temperature (a suffix) - 65 to 150 c power dissipation (package) b 16-pin cerdip c 900 mw lcc-20 d 750
www.vishay.com document number: 67952 4 s11-1003-rev. a, 23-may-11 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 dg408mil, dg409mil vishay siliconix specifications a parameter symbol test conditions unless otherwise specified temp. b typ. c a suffix - 55 c to 125 c unit v+ = 15 v, v- = - 15 v min. d max. d v al = 0.8 v, v ah = 2.4 v f analog switch analog signal range e v analog full - - 15 15 v drain-source on-resistance r ds(on) v d = 10 v, i s = - 10 ma room 40 - 100 ? full - - 125 r ds(on) matching between channels g ? r ds(on) v d = 10 v room - - 15 source off leakage current i s(off) v s = 10 v, v d = 10 v, v en = 0 v room - - 0.5 0.5 na full - - 50 50 drain off leakage current dg408 i d(off) v d = 10 v, v s = 10 v, v en = 0 v room - - 1 1 dg408 full - - 100 100 dg409 room - - 1 1 dg409 full - - 50 50 drain on leakage current dg408 i d(on) v s = v d = 10 v sequence each switch on room - - 1 1 dg408 full - - 100 100 dg409 room - - 1 1 dg409 full - - 50 50 digital control logic high input voltage v inh full - 2.4 - v logic low input voltage v inl full - - 0.8 logic high input current i ah v a = 2.4 v, 15 v full - - 10 10 a logic low input current i al v en = 0 v, 2.4 v, v a = 0 v full - - 10 10 logic input capacitance c in f = 1 mhz room 8 - - pf dynamic characteristics tran sition time t trans see figure 2 full 160 - 250 ns break-before-make interval t open see figure 4 room - 10 - enable turn-on time t on(en) see figure 3 room 115 - 150 full - - 225 enable turn-off time t off(en) room 105 - 150 charge injection q c l = 10 nf, v s = 0 v room 20 - - pc off isolation h oirr v en = 0 v, r l = 1 k ? , f = 1 mhz room - 75 - - pf source off capacitance c s(off) v en = 0 v, v s = 0 v, f = 1 mhz room 3 - - drain off capacitance dg408 c d(off) v en = 0 v, v d = 0 v, f = 1 mhz room 26 - - dg409 room 14 - - drain on capacitance dg408 c d(on) room 37 - - dg409 room 25 - - power supplies positive supply current i+ v en = v a = 0 v or 5 v full 10 - 75 a negative supply current i- full 1 - 75 - positive supply current i+ v en = v a = 0 v or 5 v room 0.2 - 0.5 ma full - - 2 negative supply current i- full - - 500 - a
document number: 67952 www.vishay.com s11-1003-rev. a, 23-may-11 5 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 dg408mil, dg409mil vishay siliconix notes a. refer to process option flowchart. b. room = 25 c, full = as determined by the operating temperature suffix. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. the algebraic convention whereby the most negative value is a mi nimum and the most positive a ma ximum, is used in this datash eet. e. guaranteed by desi gn, not subject to production test. f. v in = input voltage to pe rform proper function. g. ? r ds(on) = r ds(on) max. - r ds(on) min. h. worst case isolation occu rs on channel 4 due to pr oximity to the drain pin. stresses beyond those listed under absolute maximum ratings may cause permanent dama ge to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operatio nal sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended pe riods may affect device reliability. specifications a (single supply) parameter symbol test conditions unless otherwise specified temp. b typ. c a suffix - 55 c to 125 c unit v+ = 12 v, v- = 0 v min. d max. d v al = 0.8 v, v ah = 2.4 v f analog switch drain-source on-resistance e, f r ds(on) v d = 3 v, 10 v, i s = - 1 ma room 90 - - ? dynamic characteristics switching time of multiplexer e t trans v s1 = 8 v, v s8 = 0 v, v in = 2.4 v room 180 - - ns enable turn-on time e t on(en) v inh = 2.4 v, v inl = 0 v, v s1 = 5 v room 180 - - enable turn-off time e t off(en) room 120 - - charge injection e qc l = 1 nf, v s = 0 v, r s = 0 room 5 - - pc
www.vishay.com document number: 67952 6 s11-1003-rev. a, 23-may-11 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 dg408mil, dg409mil vishay siliconix typical characteristics (25 c, unless otherwise noted) source/drain capacitance vs. analog voltage drain leakage current vs. source/drain voltage input switching threshold vs. supply voltage drain leak age current vs. source/drain voltage (single 12 v supply) source le akage current vs. source voltage negative supply current vs. switching frequency (pf) c s, d v an al o g - analog voltage (v) 0 15 - 15 0 20 40 80 60 v+ = 15 v v- = - 15 v c d( of f) c s( o f f ) - 10 - 5 5 1 0 c d( on) dg408 i d( on) , i d( of f) (pa) i d v d or v s - drain or source v oltage (v) 0 15 - 15 - 140 - 60 20 100 60 - 20 - 100 v+ = 15 v v- = - 15 v v s = - v d for i d(off) v d = v s ( open) for i d( on) dg409 i d( of f) - 10 - 5 5 1 0 dg409 i d( on) (v) th v + v supply (v) 12 20 48 16 0.0 0.5 2.0 1.5 1.0 v an al o g - analog voltage (v) (pa) i d 12 0 10 6 2 4 8 - 60 - 40 - 20 60 40 0 20 dg408 i d( of f) dg409 i d( of f) dg409 i d( on) dg408 i d( on) v s = 0 v for i d( of f) v s = v d for i d( on) v s - source v oltage (v) 0 15 - 15 - 10 0 10 20 15 5 - 5 v+ = 15 v v- = - 15 v v+ = 12 v v- = 0 v - 10 - 5 5 1 0 i s(off) (pa) switching frequency (hz) 10k 10m 1 0 0 1k 100k 1m v su ppl y = 15 v - 100 ma - 1 ma - 100 a - 10 a - 1 a - 0.1 a - 10 ma v en = 2.4 v v en = 0 v or 5 v i-
document number: 67952 www.vishay.com s11-1003-rev. a, 23-may-11 7 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 dg408mil, dg409mil vishay siliconix typical characteristics (25 c, unless otherwise noted) positive supply current vs. switching frequency positive supply current vs. temperature (dg408) r ds(on) vs. v d and supply i supply vs. temperature charge injection vs. analog voltage r ds(on) vs. v d and supply (single supply) switchin g frequency (hz) 10k 10m 1 0 0 1k 100k 1 m v su ppl y = 15 v 100 ma 10 ma 1 ma 100 a 10 a v en = 2.4 v v en = 0 v or 5 v i + i+ (a) temperature (c) 5 15 20 10 125 - 55 85 45 5 0 v+ = 15 v v- = - 15 v v in = 0 v v en = 0 v - 35 - 15 25 65 105 r ds(on) ( ) v d - drain v oltage (v) 0 40 100 60 80 120 20 - 20 - 12 - 8 - 4 0 4 8 1 2 1 6 2 0 - 16 5 v 8 v 10 v 12 v 20 v 15 v i+, i- temperature (c) 125 - 55 85 45 5 v su ppl y = 15 v v a = 0 v v en = 0 v i+ - (i-) 100 a 1 a 100 na 10 na 1 na 100 pa 10 pa 10 a - 35 - 15 25 65 105 q (pc) v s - source v oltage (v) - 10 30 50 90 70 40 0 80 60 20 10 0 15 - 15 - 10 - 5 5 1 0 v+ = 15 v v- = - 15 v v+ = 12 v v- = 0 v c l = 10 000 pf v in = 5 vp-p v d - drain voltage (v) 22 0 0 40 100 60 140 160 80 120 20 4 8 12 16 20 v+ = 7.5 v 10 v 12 v 15 v 20 v 22 v v- = 0 v r ds(on) ( )
www.vishay.com document number: 67952 8 s11-1003-rev. a, 23-may-11 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 dg408mil, dg409mil vishay siliconix typical characteristics (25 c, unless otherwise noted) r ds(on) vs. v d and temperature off isolation and crosstalk vs. frequency switching time vs. bipolar supply r ds(on) vs. v d and temperature (single supply) insertion loss vs. frequency switching time vs. single supply r ds(on) ( ) v d - drain voltage (v) 0 15 - 15 0 40 60 80 50 10 70 30 20 v+ = 15 v v- = - 15 v 125 c 85 c 25 c - 55 c - 10 - 5 5 1 0 - 40 c 0 c (db) f - frequency (hz) 10k 10m - 30 - 70 - 90 - 50 1 0 0 1k 100k 1m - 110 100m - 130 - 150 v+ = 15 v v- = - 15 v r l = 1 k of f-isolation crosstalk t (ns) v su ppl y (v) 10 12 14 16 18 20 22 60 80 100 120 140 t off(en) t on(en) t trans r ds(on) ( ? ) v d - drain voltage (v) 4 0 10 30 50 70 90 110 130 v+ = 12 v v- = 0 v - 55 c - 40 c 0 c 125 c 85 c 25 c 2681012 l oss (db) f - frequency (hz) 10m - 5 - 2 1 - 1 0 - 4 - 3 - 6 v+ = 15 v v- = - 15 v ref. 1 v rms r l = 50 r l = 1 k 1 0 1 0 0 1k 10k 100k 1 m 100m t (ns) v supply (v) 15 8 100 150 225 175 200 250 125 91214 13 11 10 275 t trans t off(en) t on(en)
document number: 67952 www.vishay.com s11-1003-rev. a, 23-may-11 9 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 dg408mil, dg409mil vishay siliconix schematic diagram (typical channel) fig. 1 test circuits fig. 2 - transition time en a 0 s 1 d v+ s n v- decode/ drive level shift v- v+ v ref a x gnd v+ a 1 a 0 a 2 a 1 a 0 + 15 v - 15 v en v+ v- gnd d 35 pf v o s 1 s 2 - s 7 s 8 50 300 10 v 10 v + 15 v - 15 v en v+ v- gnd 35 pf v o s 1 s 1a - s 4a , d a s 4b 50 300 10 v 10 v d b logic input switch output v s8 v o t trans t r < 20 ns t f < 20 ns s 8 on s 1 on t trans 0 v v s1 50 % 90 % 90 % 3 v 0 v dg408 dg409
www.vishay.com document number: 67952 10 s11-1003-rev. a, 23-may-11 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 dg408mil, dg409mil vishay siliconix test circuits fig. 3 - enable switching time fig. 4 - break-before-make interval logic input switch output v o t r < 20 ns t f < 20 ns 3 v 0 v 0 v t off(en) t on(en) 50 % 90 % 10 % v o en s 1 s 2 - s 8 a 0 a 1 a 2 50 1 k v o v+ gnd v- d - 5 v 35 pf - 15 v + 15 v s 1b s 1a - s 4a , d a s 2b - s 4b d b en a 0 a 1 50 1 k v o v+ gnd v- - 5 v 35 pf - 15 v + 15 v dg408 dg409 50 % 80 % logic input switch output v o v s t open t r < 20 ns t f < 20 ns 0 v 3 v 0 v en v+ gnd v- + 5 v 35 pf - 15 v + 15 v + 2.4 v a 2 d b , d all s and d a 300 v o 50 a 1 a 0 dg408 dg409
document number: 67952 www.vishay.com s11-1003-rev. a, 23-may-11 11 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 dg408mil, dg409mil vishay siliconix test circuits fig. 5 - charge injection fig. 6 - off isolation fig. 8 - insertion loss fig. 7 - crosstalk fig. 9 - source drain capacitance a 0 en a 1 a 2 v o v+ gnd v- d - 15 v + 15 v r g s x c l 10 nf channel select 3 v 0 v off on logic input switch output v o v o is the measured voltage due to charge transfer error q, when the channel turns off. q = c l x v o off r l 1 k v o v+ gnd v- - 15 v + 15 v a 2 d a 1 a 0 s 8 s x v s en r g = 50 off isolation = 20 log v out v in v in r l 1 k a 2 v o d r g = 50 insertion loss = 20 log v out a 1 v in a 0 v s s 1 v+ gnd v- - 15 v + 15 v en r l 1 k v o v+ gnd v- - 15 v + 15 v a 2 d a 1 a 0 s 8 s x v s en r g = 50 crosstalk = 20 log v out v in v in s 1 f = 1 mhz s 1 d en + 15 v - 15 v gnd v+ v- meter hp4192a impedance analyzer or equivalent s 8 a 1 a 2 a 0 channel select
www.vishay.com document number: 67952 12 s11-1003-rev. a, 23-may-11 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 dg408mil, dg409mil vishay siliconix application hints overvoltage protection a very convenient form of over voltage protection consists of adding two small signal diodes (1n4148, 1n914 type) in series with the supply pins (see figure 10). this arrangement effectively blocks the flow of reverse currents. it also floats the supply pin above or below the normal v+ or v- value. in this case the overvoltage signal actually becomes the power supply of the ic. from the poin t of view of the chip, nothing has changed, as long as the difference vs - (v-) does not exceed + 44 v. the addition of these diodes will reduce the analog signal range to 1 v below v+ and 1 v above v-, but it preserves the low channel resistance and low leakage characteristics. fig. 10 - overvoltage protection using blocking diodes fig. 11 vishay siliconix maintains worldwide manufa cturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qu alified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?70062 . 1n4148 dg408 d v- v+ 1n4148 s x v g en a 0 a 1 + 15 v (mux on-off control) analog inputs (outputs) clock in nc enable in analog output (input) + 15 v - 15 v dg408 d en gnd dm7493 v+ v- nc gnd + 15 v analog inputs (outputs) analog outputs (inputs) + 15 v - 15 v dg409 gnd v+ v- differential differential clock in nc gnd + 15 v nc 6 reset enable j k clk j k clk clear clear q s 5 s 7 s 6 s 8 s 1 s 3 s 2 s 4 s 1a s 3a s 2a s 4a s 1b s 3b s 2b s 4b d a d b a 0 a 1 a 2 b in a in r 01 r 02 q b q c q d q a 1/2 mm74c73 1/2 mm74c73 q q q 8-channel sequential multiplexer/demultiplexer differential 4-channel sequential multiplexer/demultiplexer
e 1 e q 1 a l a 1 e 1 b b 1 l 1 s c e a d 12 3 4 5 6 7 8 16 15 14 13 12 11 10 9 package information vishay siliconix document number: 71282 03-jul-01 www.vishay.com 1
dim min max min max a 4.06 5.08 0.160 0.200 a 1 0.51 1.14 0.020 0.045 b 0.38 0.51 0.015 0.020 b 1 1.14 1.65 0.045 0.065 c 0.20 0.30 0.008 0.012 d 19.05 19.56 0.750 0.770 e 7.62 8.26 0.300 0.325 e 1 6.60 7.62 0.260 0.300 e 1 2.54 bsc 0.100 bsc e a 7.62 bsc 0.300 bsc l 3.18 3.81 0.125 0.150 l 1 3.81 5.08 0.150 0.200 q 1 1.27 2.16 0.050 0.085 s 0.38 1.14 0.015 0.045 0 15 0 15 ecn: s-03946?rev. g, 09-jul-01 dwg: 5403
d l 1 e b l e a 1 a 28 1 2 packaging information vishay siliconix document number: 71290 02-jul-01 www.vishay.com 1

dim min max min max 1.37 2.24 0.054 0.088 1.63 2.54 0.064 0.100 0.56 0.71 0.022 0.028 8.69 9.09 0.342 0.358 8.69 9.09 0.442 0.358 1.27 bsc 0.050 bsc 1.14 1.40 0.045 0.055 1.96 2.36 0.077 0.093 ecn: s-03946?rev. b, 09-jul-01 dwg: 5321
package information www.vishay.com vishay siliconix revison: 27-jul-15 1 document number: 74786 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 flat pack: 16 leads dim. millimeters inches min. max. min. max. a 1.52 2.54 0.060 0.100 b 0.38 0.48 0.015 0.019 c 0.10 0.15 0.004 0.006 d 9.91 10.41 0.390 0.410 e 6.60 7.11 0.260 0.280 e2 4.45 4.95 0.175 0.195 e3 0.76 1.27 0.030 0.050 e 1.27 bsc 0.050 bsc l 7.62 8.89 0.300 0.350 q 0.66 1.14 0.026 0.045 s - 1.14 - 0.045 s1 0.013 - 0.005 - ecn: s15-1674-rev. d, 27-jul-15 dwg: 5343 d s s 1 d b e l e3 e2 c q a 16 15 14 13 12 11 10 9 12 3 4 5 6 7 8
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